AMLCDs with a flat form factor have a demonstrated potential for reducing the weight, volume, power requirement, and cost, as well as for providing enhanced reliability compared to those factors of conventional cathode ray tube (CRT) displays. However, one significant problem with AMLCD panels has been the difficulty in achieving grayscale with adequate viewing angle. A number of display applications require wide-viewing angle grayscale and, without this, applications of AMLCD panels will be severely restricted.
In related art, a method for generating grayscales in an AMLCD having a wide viewing angle and using a half-tone approach, already has been developed. Half-toning is accomplished by subdividing each pixel into a number of subpixels, and incorporating a control capacitor in series with each subpixel. The control capacitors act as voltage dividers. By using a proper choice of values for the control capacitors, the voltages across the subpixels are varied such that, as each subpixel is selected to be turned-on, the voltage across it is at or above saturation voltage, while the voltages across the unselected subpixels are at or below threshold voltage. For any gray level selected by varying the thin film transistor (TFT) source voltage, at the most, only one subpixel will be between the threshold voltage (V.sub.th) and saturation voltage (V.sub.s). This significantly reduces the viewing angle dependence of the pixel luminance and grayscale. The control capacitor capacitance that determines a particular voltage value of the selected pixel, is adjusted by variation in its area or thickness of the dielectric. In related art, the control capacitors and the active matrix array are fabricated at the same time on the same substrate.
One major problem with the related art approach is that design and processing trade-offs are required when fabricating an active matrix array having control capacitors on the same substrate. These trade-offs result in a detrimental effect on performance and yield. The active matrix substrate includes several thin films and processing steps. In the conventional active matrix substrate fabrication, the thin films, their thicknesses and the processing parameters are selected to optimize the performance and yield of the TFTs, and thus of the display. However, incorporation of control capacitors on the same substrate results in non-optimum film thicknesses or processing conditions for the TFT switching devices and/or the control capacitors.
The following instance illustrates a problem of related-art fabrication. The control capacitors, utilizing area variation as means for capacitance variation, require a second transparent conductive electrode, which is generally indium tin oxide (ITO). The second ITO layer is deposited after the TFT array fabrication is complete. For optimum ITO deposition conditions, the substrate will have to be heated in excess of 300.degree. Centigrade (C). But this high temperature cycle degrades the properties of the a-Si TFTs.
To minimize the total number of process steps in fabrication, the TFT passivation layer is also used as a dielectric in the control capacitors with area variation. The choice of the dielectric and its thickness for the TFT passivation layer are determined by the dielectric/semiconductor interface properties and the step coverage issues. However, the choice of the dielectric and its thickness for the control capacitors is determined by the needed capacitance values for the control capacitors. These requirements of the dielectric and its thickness for TFTs and the control capacitors are usually not in agreement, and thus trade-offs need to be made if the same dielectric layer is to be used for TFT passivation as well as for control capacitors. Similarly, while the dielectric in the TFT structure can be used in the fabrication of control capacitors with thickness variation, the dielectric thickness requirements for the TFT structure and the control capacitors are quite different.
Another problem is that the conventional approach of the related art increases the number of processing steps (masking levels) for the TFT substrate. A greater number of steps increases the defect levels in the display and lowers the manufacturing yield. Negligible defect levels and high manufacturing yields are essential for the success of AMLCD panels. So, because the yields and costs are adversely affected as the number of masking levels and the process steps is increased, the related art requires design and process trade-offs to minimize the number of mask levels required for the fabrication of the active matrix substrates. Accordingly, a need exists to develop a method of manufacturing the half-tone grayscale displays with control capacitors that does not require design and process trade-offs with resulting performance and yield degradation. The present invention responds to that need by separating the control capacitors from the active matrix substrate and having the active matrix substrate fabrication be strictly conventional. The control capacitors are fabricated on a second substrate containing the common electrode. The separation of the active matrix array and the control capacitor array between the two display glass substrates, permits each array to be fabricated with conventional techniques under its own optimum conditions to achieve high performance and yield, and low cost.